The present invention relates to integrated circuit device testers, and more particularly to an apparatus and method for providing electrical connections between ball grid array (BGA) packaged integrated circuits under test and the integrated circuit device testers.
Integrated circuit (IC) devices typically include an IC chip that is housed in a plastic, ceramic or metal package. The IC chip includes an integrated circuit formed on a thin wafer of silicon. The package supports and protects the IC chip and provides electrical connections between the integrated circuit and an external circuit or system.
There are several package types, including ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, and plastic quad flat packs. Each of the package types is typically available in numerous sizes. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and also in accordance with a customer""s requirements.
FIGS. 1 and 2 show bottom and side sectional views, respectively, of a typical BGA IC 100 including an IC chip 110 mounted on an upper surface 122 of a package substrate 120. Electrical connections between bonding pads 115 of IC chip 110 and contact pads 125 formed on upper surface 122 of substrate 120 are provided by bond wires 130. A plurality (sixty-four shown) of solder balls (sometimes referred to as solder bumps) 126 extend from a lower surface 127 of substrate 120 which are electrically connected to the conductive lines (not shown) 120 and conductive vias 128 that are provided on substrate 120. Electrical signals travel between each solder ball 126 and one bonding pad 115 of IC chip 110 along an associated conductive line/via 128 and bond wire 130. For example, a test signal applied to solder ball 126-A is transmitted on conductive via 128A to contact pad 125A, and from contact pad 125A along bond wire 130A to bonding pad 115 of substrate 110. A cover 129, such as a cap or xe2x80x9cglob topxe2x80x9d, is placed or formed over IC chip 110 and bond wires 130 for protection.
IC testing systems are used by IC manufacturers to test their ICs before shipping to customers. IC testing systems typically include a device tester, a device handler and an interface structure. A device tester is an expensive piece of computing equipment that transmits test signals via tester probes to an interface structure. The interface structure transmits signals between the leads of an IC under test and the device tester. A device handler is an expensive precise robot for automatically moving ICs from a storage area to the interface structure and back to the storage area. Such testing systems are well known.
FIGS. 3(A) and 3(B) show side and top views of a conventional interface structure 200 that is disclosed in U.S. Pat. No. 5,955,888.
Interface structure 200 includes a printed circuit board (PCB) 210 having mounted thereon a plurality of pogo pins 220, a contactor body 240 mounted on PCB 210, and a nesting member 270 that is mounted over contactor body 240. PCB 210 includes connection structures (not shown) for receiving test signals from a device tester, and conductive lines (also not shown) for transmitting signals between the connection structures and pogo pins 220. Contactor body 240 includes four walls that are formed into a generally square or rectangular frame through which pogo pins 220 extend. A non-conductive plate 250 is mounted on an upper surface of contactor body 240 for aligning pogo pins 220 such that a tip 224 of each pogo pin 220 is aligned with a corresponding through-hole 276 formed in nesting member 270. Nesting member 270 is slidably mounted on shoulder bolts 245 that extend upward from contactor body 240, and is biased away from contactor body 240 by coil springs 260. Mounted on an upper surface 272 of nesting member 270 is a fixed (permanently attached) series alignment structures 280 that define an IC receiving (test) area 275, which includes through-holes 276.
Referring to FIG. 3(B), during a test procedure a BGA IC 100 is lowered into IC receiving area 275 of nesting member 270 by a device handler (not shown). Alignment structures 280 are formed with slanted walls 282 that facilitate xe2x80x9croughxe2x80x9d alignment by causing BGA IC 100 to slide into IC receiving area 275. Subsequently, each solder ball 126 becomes engaged with an associated through-hole 276, which are chamfered to provide xe2x80x9cfinexe2x80x9d alignment of BGA IC 100 relative to pogo pins 220. BGA IC 100 and nesting member 270 are then pressed downward (as indicated by the arrow) to compress springs 260 until tips 224 of pogo pins 220 contact solder balls 126, thereby providing electrical connections between a testing device (not shown) connected to pogo pins 220 and IC device 100 for the testing procedure.
A problem associated with conventional interface apparatus 200 is that each apparatus can only support a single BGA IC package size (i.e., the peripheral size of the package substrate). Accordingly, an IC manufacturer utilizing several BGA IC package sizes must purchase a separate interface apparatus for each BGA IC package, thereby increasing total device testing costs.
What is needed is a method for testing different sized BGA ICs using a single interface apparatus.
The present invention is directed to testing BGA ICs having various package sizes using a single interface apparatus and a set of inexpensive removable/replaceable adapters, thereby significantly reducing costs associated with testing an entire line of BGA ICs by eliminating the need for individual interface apparatus for each BGA IC.
In accordance with an embodiment of the present invention, an interface apparatus includes a nesting member having a central test area, a positioning member surrounding the test area, and a plurality of removable adapters that are held by the positioning member. Each removable adapter includes a central opening that is sized to receive a ball grid array integrated circuit (BGA IC) having a corresponding package size.
In accordance with another embodiment of the present invention, a method for testing BGA ICs having different package sizes using a single interface apparatus includes testing a first BGA IC having a first package size using a first adapter, and then testing a second BGA IC having a second package size using a second adapter. For example, during a first test procedure, a first adapter having a relatively small central opening is mounted on the nesting member of the interface apparatus such that a relatively small portion of the test area is exposed through the central opening. A relatively small first BGA IC is then inserted manually or by a handler through the central opening of the first adapter, and is pressed downward such that the solder balls of the first BGA IC contact a relatively small number of the pogo pins located under the nesting member. Test signals are then transmitted to and from the first BGA IC on the relatively small number of pogo pins using known methods. The first BGA IC and the first adapter are then removed and replaced with a second adapter having a relatively large central opening. A second test procedure is then performed by inserting a relatively large BGA IC through the central opening of the second adapter, and pressing downward such that the solder balls of the second BGA IC contact a relatively large number of the pogo pins. Test signals are then transmitted to and from the second BGA IC using the relatively large number of pogo pins.